High performance analog to digital converters (ADCs) are increasingly required for precise digital processing of analog signals. Applications include receiving low-level current signal outputs from photo-detectors such as in imaging systems. Such imaging systems can include, for example, X-ray imaging systems. In a further application, the X-ray technology is combined with photo-detectors in a ring configuration to form computed tomography (CT) scanners used in medical diagnostics, for example.
Recent improvements for analog to digital converters (ADCs) include the use of resettable delta-sigma ADCs. In such an ADC, the memory elements are all reset before each new conversion. The input signal is assumed to be stable during each conversion cycle. This input signal is repeatedly sampled, each sample is compared to a reference voltage level to determine a corresponding data bit, the data bits are quantized by a clocking sampling circuit to create a plurality of conversion samples, and the conversion samples are averaged. The repeated sampling is done to reduce or eliminate the effects of noise such as quantization noise and thermal noise on the digital representation of the analog signal. As the analog input does not change during a conversion cycle, the input voltage can be sampled on a capacitor and placed in feedback around a driver amplifier. The output of the driver amplifier can then drive the switched sampling capacitor of the first stage of an ADC.
FIG. 1A depicts in a simple block diagram an input stage 10 for an ADC of the prior art. In FIG. 1A, an input “Vin” is sampled onto the capacitor C1. The output of the driver circuit is a voltage “Vin” which is the input for the remainder of the circuit 10.
As is known to those skilled in the art, the input stage to an ADC can be implemented as a switched capacitor sampling stage. Here the sampling capacitor labeled Csamp is coupled to the Vin voltage output of the driver circuit 13 and capacitor C1 by a two phase switching circuit. The operation of the switching circuitry is now described. Assume all switches 11, 15, 17 and 21 in FIG. 1A are initially open. Switch 11 and switch 17 are closed in a sampling operation responsive to a first periodic control signal PHI_1, and when these switches are closed, capacitor Csamp receives the voltage Vin (minus a supply voltage Vss (or ground)). In order to subsequently transfer the stored voltage from capacitor Csamp into the rest of the converter circuitry ADC 19, the switch 11 and switch 17 are opened, and switches 15 and 21 subsequently closed. These switches 15 and 21 are controlled by a second periodic control signal PHI_2, and when PHI_2 is active, the voltage on capacitor Csamp is transferred to the ADC 19. ADC 19 can include a comparator and a quantizer for clocking samples of the voltage stored on Csamp and for outputting a plurality of digital bits that represent a voltage level for the analog input. An average of the oversampled data can be taken in a decimator to get an accurate digitized signal corresponding to the analog input signal.
The control signals PHI_1 and PHI_2 are periodic non-overlapping control signals that repeatedly sample the output voltage of the integrator circuit, labeled voltage Vin in FIG. 1A, into the ADC 19 during an analog conversion cycle. FIG. 1B illustrates in a simple timing diagram the timing of periodic control signals PHI_1 and PHI_2. In operation, the signals repeatedly cause the switches to close and thus control the sampling of voltage Vin into capacitor Csamp, and the transfer from Csamp into the ADC 19. Importantly, the signals PHI_1 and PHI_2 must not overlap, e.g., must not be active at the same point in time. In the illustrative example shown in FIG. 1B, the signals have a 50% duty cycle, but other duty cycles can be used. Typically the duty cycles for PHI_1 and PHI_2 can be similar or equal, but alternatives with asymmetric or non-equal duty cycles can also be used.
In the switched capacitor sampling stage 10, a prior known solution operates the sampling switch 11 using a bootstrap circuit. Using a bootstrap circuit with a bootstrap capacitor places a higher voltage at the gate during a turn on operation for an N-type MOS transistor that is used as the sampling switch 11, and so ensures rapid turn-on of the transistor. FIG. 2 depicts, for example, a prior art solution using a transistor M1 configured as the sampling switch 11 in FIG. 1, operated with a bootstrap capacitor Cb. During the first phase, when the control signal PHI_2 is active, switches 31 and 33 are closed and capacitor Cb is charged to VDD−VEE, where VDD is a positive supply voltage, and VEE is the most negative supply voltage in the system, which can be zero volts for example. At the same time switch 41 is closed and ensures that N-type MOSFET M1 is turned off by placing VEE at the gate terminal.
In the second phase of the operation of the circuit of FIG. 2, control signal PHL_1 is high and switches 35, 39 are closed while switches 31, 33 and 41 are opened. The voltage stored on bootstrap capacitor Cb, which is voltage VDD when VEE is zero volts, is now added to the input voltage Vin so that the voltage on the gate terminal of transistor M1 is now boosted to the input voltage Vin+VDD, turning on the transistor M1. Vin is also at the source terminal of transistor 43. The transistor M1 is turned on and so acts as the “closed” switch 11 in FIG. 1A, and the output voltage Vout receives the voltage Vin while the transistor M1 is turned on.
In order to provide high performance in the ADC circuit that incorporates the bootstrap circuit and the sampling switch, the circuit must have a more or less constant resistance, so as to provide highly linear results. Importantly the resistance should be independent of the voltage Vin, as this integrator circuit output voltage varies with the analog voltage being converted. The on resistance Rdson for the transistor M1 is proportional to the gate to source voltage (Vgs) for the transistor. While transistor M1 in FIG. 2 is turned on, the gate voltage is at (Vin+VDD). The source voltage is at Vin, so the voltage Vgs for transistor M1 is (Vin+VDD)−Vin, or simply VDD. This is an important feature of the prior known solution for switched capacitor bootstrap circuit 30 shown in FIG. 2. Because the gate to source voltage Vgs of transistor M1 is independent of the input voltage Vin, which varies with the analog input voltage, the circuit operates to provide a more linear performance for the ADC by presenting a constant on-resistance over many cycles.
In operation of the ADC circuit including the bootstrap circuit of FIG. 2, the input voltage is sampled onto the capacitor C1 of the driver circuit 13 once per conversion cycle, for example in a resettable sigma delta ADC, and then the switched capacitor circuit including the sampling capacitor Csamp samples that Vin voltage value many times. When the prior known solution bootstrap circuit 30 shown in FIG. 2 is used, the driver 13 has to drive the capacitor Cb each time the control signal PHI_1 is active. The driver 13 is also coupled to drive the bottom plate of the bootstrap capacitor Cb, which has a large parasitic capacitance. Since the periodic sampling occurs many times for each analog conversion cycle, this is a substantial load on the driver amplifier 13 and consumes power for each of the sampling cycles of the ADC operations. Further the driver 13 has to charge the gate capacitance of the transistor M1 for each cycle, and because the input voltage Vin is coupled to the gate terminal, some non-linear effects still occur. The need to drive the bottom plate of the bootstrap capacitor and the gate of the MOS transistor, and the corresponding parasitic capacitances, each time PHL_1 is active, causes increased power dissipation. Further, the gate capacitance and the bottom plate of the bootstrap capacitor Cb are charged to a voltage such as VEE and VDD respectively, in the off phase, and in the on phase (PHI_1 is active), these parasitic capacitances cause large load steps on the driver.
Improvements in the bootstrap circuitry for switched capacitor sampling circuits, such as for the input stage of ADCs, are therefore needed to address the deficiencies and the disadvantages of the prior known approaches. Solutions are needed that reduce power, and which improve the performance of the circuits.